1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to integrated circuit designs adapted so as to be more readily fabricated.
2. Description of the Prior Art
It is known to fabricate integrated circuits via lithographic processes whereby an integrated circuit is built up of a plurality of layers formed one on top of another. One or more of the layers typically formed includes a contact layer which provides electrical contacts to underlying layers, such as polysilicon layers or diffusion layers. It is also known to form layers including vias for providing electrical connections to underlying layers. As process geometries have decreased in size, it has become difficult to form masks capable of printing a full lithographic layer in one operation. In order to address this issue, it is known to utilise so called “double patterning” whereby two pattern layers are printed in turn and which together form a lithographic layer to be utilised for controlling a further process, such as etching, deposition etc. By splitting the formation of the lithographic layer into two or more printed pattern layers it becomes possible to space the features of the mask further apart in the different pattern layers enabling these masks to be more readily formed and printed.
It is also know within the field of integrated circuits to form circuits of multiple devices in which the performance characteristic of the circuit formed is dependent upon how well matched are the devices which combine to form that circuit. As an example, when forming sense amplifiers or operational amplifiers on an integrated circuit, it is important that various of the devices (transistors) which form those circuits have closely matching characteristics so as to avoid a degradation of the performance characteristic of the circuit as a whole, e.g. mismatched devices within an operational amplifier may produce an undesirably high offset voltage or mismatched devices within a sense amplifier may make the sense amplifier disadvantageously insensitive to one polarity of voltage difference compared to another polarity of voltage difference. This sensitivity to mismatched devices is becoming greater as process geometries fall in size since there is a general trend for increased manufacturing variance as process geometry falls in size. Such degradation in the performance characteristics of the circuits formed within an integrated circuit can be sufficient to reduce yield and/or overall performance in an unacceptable manner. This problem is also becoming worse as device geometries become smaller.